The present invention relates to a high breakdown voltage semiconductor device using a silicon on insulator (SOI) substrate, and in particular, has an object of being used in a power conversion integrated circuit represented by a high voltage integrated circuit (HVIC). It may mainly be utilized in a lateral double diffused MOSFET (LDMOSFET) of a 100 volt to 1200 volt high breakdown voltage class.
In recent years, accompanying a demand for a high breakdown voltage of a power IC, an SOI substrate which can completely isolate elements using trench dielectric isolation and an insulating film has attracted attention. By forming a high voltage power conversion integrated circuit on the SOI substrate, advantages include preventing a malfunction due to a parasitic element when switching, preventing interference due to noise, a reduction of parasitic capacity, and the like. Also, as it is possible to apply trench dielectric isolation to an edge structure or high voltage junction termination (HVJT) structure of each device in the integrated circuit, an advantage of a chip size shrink of the integrated circuit itself can also be expected.
FIG. 12 is a sectional view of a main portion of a heretofore known high breakdown voltage semiconductor device. The heretofore known high breakdown voltage semiconductor device 950 shown in FIG. 12 is such that, a dielectric layer 901 being provided on the upper surface of a support substrate 900, an n− type semiconductor layer 902, which is formed of a semiconductor substrate, is included on the upper surface of the dielectric layer 901. The dielectric layer 901 dielectrically isolates the support substrate 900 and n− type semiconductor layer 902, and insulating isolation in a horizontal direction inside the n− type semiconductor layer 902 is compartmentalized by trench dielectric isolation with a silicon dioxide film 904 packed into a trench 903 formed in the n− type semiconductor layer 902. Within a predetermined range in the compartmentalized n− type semiconductor layer 902, taking the n− type semiconductor layer 902 to be a drain-drift region 902, a high concentration drain n+ layer 913, and an n-type buffer layer 912 with a resistance higher than that of the drain n+ layer 913, are included in a central portion of the upper surface of the drain-drift region 902, and a p-type well diffusion layer 911, and a source n+ layer 914 inside the p-type well diffusion layer 911, are each formed so as to be separated from the n-type buffer layer 912, and to encircle the n-type buffer layer 912. Also, there being provided the source n+ layer 914 and p-type well diffusion layer 911, and a gate electrode 910 on the drain-drift region 902 across an insulating film, a source electrode 908 and drain electrode 909 are provided on the source n+ layer 914 and drain n+ layer 915 respectively, and the source electrode 908 and drain electrode 909 are mutually insulated by a field oxide film 905, an interlayer insulating film (ILD: Inter Layer Dielectrics) 906, and passivation film 907. Also, field plate electrodes are provided on the source n+ layer 914 and drain n+ layer 913, jutting toward each other above the drain-drift region 902. In FIG. 12, the source electrode 908 and drain electrode 909 configure the field plate electrodes by extending on the interlayer insulating film 906.
On fixing the support substrate 900, source electrode 908, and gate electrode 910 at a ground potential, and applying a positive bias to the drain electrode 909, a depletion layer extends from the p-n junction between the p-type well diffusion layer 911 and n− type semiconductor layer 902 of the semiconductor device 900. Also, as the support substrate 900 is fixed at the ground potential at the same time, a depletion layer also extends from the interface of the dielectric layer 901 and n− type semiconductor layer 902. Therefore, depletion layers extend from the horizontal direction and vertical direction inside the n− type semiconductor layer 902, and the surface electric field of the drain-drift region 902 is reduced. This advantage is generally called a RESURF (RESURF: Reduced Surface Field) effect.
By making a distance Ld between the n-type buffer layer 912 and p-type well diffusion layer 911 of the drain-drift region 902 sufficiently long, adjusting to an optimum impurity concentration, and optimizing the length by which the field plate electrodes jut out, the design is such that the surface electric field is reduced, there is no electric field concentration at the p-n junction, and also, no avalanche breakdown occurs on the semiconductor substrate surface, even when a high voltage is applied to the drain electrode 909.
At this time, the avalanche breakdown occurs at the interface of the drain-drift region 902 and dielectric layer 901. A breakdown voltage Vbr of this kind of high breakdown voltage semiconductor device when satisfying the RESURF conditions is expressed, converting a Poisson equation, as Expression 1.Expression 1Vbr=Ecr*(d/2+Tox*∈si/∈ox)  (1)
Herein, Ecr is a critical electric field, d is the thickness of the n− type semiconductor layer 902 (unit: μm), and Tox is the thickness of the dielectric layer 901 (unit: μm). Herein, in a case in which the n− type semiconductor layer 902 is formed of silicon, and the dielectric layer 901 of a silicon dioxide film, the breakdown voltage Vbr is such that, when substituting Ecr=3E5 (V/cm), d=20 μm, Tox=5 μm, ∈si=11.7, and ∈ox=3.9, Vbr=750V.
Generally, in a case in which the breakdown voltage of a level shifter and high breakdown voltage bootstrap diode mounted in an HVIC has a product specification of 600 volts, taking into consideration a resistivity fluctuation of the n− type semiconductor layer 902, a fluctuation in thickness of the dielectric layer 901, and furthermore, the actual breakdown voltage of a power MOSFET, and the like, controlled by the HVIC, a breakdown voltage in the range of at least 750V is required.
According to Expression 1, in order to increase the breakdown voltage of the high breakdown voltage semiconductor device, it is sufficient to carry out an increase of the thickness d of the n− type semiconductor layer 902, or of the thickness Tox of the dielectric layer 901, but with regard to the thickness d of the n− type semiconductor layer 902, as there are restrictions in manufacturing processes such as an etching of the trench which compartmentalizes the elements in a horizontal direction on the n− type semiconductor layer 902, and an oxide film embedding, a range of d=10 to 20 μm is a realistic value. Also, there is a problem in that, in the case of an SOI substrate using a layer bonding method, the greater the thickness Tox of the dielectric layer 901, the greater the wafer warpage in the IC processing manufacturing process, and a problem in that, as there is an accompanying increase in the deposition time of the dielectric layer 901 in a high temperature oven, the cost of the SOI substrate increases. In addition, as increasing the thickness of the dielectric layer 901 reduces the extension of the depletion layer extending from the junction surface of the dielectric layer 901 and n− type semiconductor layer 902, the RESURF effect decreases, and the high breakdown voltage semiconductor device surface electric field becomes steep, meaning that the breakdown voltage decreases. Therefore, even when estimating on the thick side, a range of Tox=4 to 5 μm is a realistic value for the thickness of the dielectric layer 901.
However, when attempting to integrate the high breakdown voltage semiconductor device 900, including the thick dielectric layer 901 and thick n− type semiconductor layer 902 optimized for a high breakdown voltage application in this way, in one chip in order to mount it in a power conversion integrated circuit such as the HVIC, it is necessary to connect it from the drain electrode 909, with an aluminum wire 917 or the like, to an unshown high voltage region, which is a high side drive circuit. When attempting to carry out this connection by passing the wire from the central electrode (the drain electrode 909) of the high breakdown voltage semiconductor device over the peripheral semiconductor region (the source n+ layer 914 and p-type well diffusion layer 911), as described in Japanese Patent No. 3489362, the potential of the drain-drift region 902 is drawn to the potential of the drain electrode 909, and an electric field concentrates locally in the vicinity of the p-type well diffusion layer 911, meaning that there is a problem in that, not only does a uniform breakdown voltage design fall apart, but also the region below the wire is of a low voltage, an avalanche breakdown occurs, and the breakdown voltage decreases.
Therein, normally, in order to carry out a stable high potential wiring from a semiconductor device formed in a dielectrically isolated region to an adjacent or separate dielectrically isolated region, the kind of high potential wiring connection method using a bonding wire shown in JP-A-2006-313828 and Japanese Patent No. 4020195 is implemented. In JP-A-2006-313828 and Japanese Patent No. 4020195, a method is proposed wherein a separate dielectric body is disposed adjacent to the dielectric layer in a lamination direction, and the breakdown voltage of the semiconductor device is kept high. However, the configurations described in JP-A-2006-313828 and Japanese Patent No. 4020195 involve a complicated rear surface processing process which increases costs.